Computing devices include silicon hardware, e.g., a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), Integrated Circuits (ICs), an Application Specific Integrated Circuit (ASIC), a memory controller, etc. The manufacturing of the silicon hardware is often based on highly complex logic designs. The manufacture of silicon hardware typically requires verification of the logic design through testing in order to verify that the circuits within the silicon hardware are designed properly. Also, once the verified logic design is used to build the silicon hardware, the newly manufactured silicon hardware is validated through one or more tests in order to enhance manufacturing quality. Thus, the silicon hardware undergoes both pre-silicon and post-silicon testing.
FIG. 1 shows a flowchart including typical operations involved with manufacture of silicon hardware. A first operation includes generating a logic design for the silicon hardware (Step 20). The logic design may be written in a Hardware Definition Language (e.g., Verilog), and may be written at a particular level of abstraction, e.g., at gate level, where individual gates (such as AND gates) are detailed, or at Register Transfer Level (RTL). Then, the logic design is instrumented (Step 22). The instrumentation added to the logic design enables testing to obtain values of some or all of the state elements of the logic design and silicon hardware for testing purposes. For example, the logic design may include an AND gate, and the value of the output of the AND gate may be of interest at a particular point during testing. Therefore, the instrumentation may be used to obtain the value of that particular state element during testing, both in pre-silicon and post-silicon testing.
Then, the instrumented logic design is verified through testing (Step 24). For example, two versions of the instrumented logic design may be simulated on two different simulators, where one version of the instrumented logic design has already been verified as correct. Simulations may be cycle-by-cycle, or may be event-driven. In a cycle-by-cycle simulation, values of state elements may vary from cycle to cycle, depending on the stimuli used during the test. For example, in the span of 5 cycles, the value of a particular AND gate output may alternate between “1” and “0.” Thus, if the AND gate is instrumented, the values of the AND gate output for the 5 cycles may be the following sequence of numbers: “01010.”
Then, once the instrumented logic design is verified through testing, the silicon hardware is manufactured using the instrumented logic design (Step 26). Manufacture of the silicon hardware may take place some time after, and/or at a different location from when and where the instrumented logic design was tested. Once the silicon hardware has been manufactured, the silicon hardware is validated through testing (discussed in more detail below) (Step 28), and then shipped to various customers (Step 30).
Validation of the newly manufactured silicon hardware may be implemented via multiple mechanisms. For example, the silicon hardware may execute a program that includes test instructions designed to “more or less” exhaustively exercise each functional unit of the silicon hardware. However, instrumenting enough of the state elements of the silicon hardware in order to read enough values of state elements may be a challenge in complex silicon hardware. Scan chaining is one technique used to obtain values of state elements that may be hidden during testing.
FIG. 2 shows a flowchart including operations used in scan chaining. A first step includes chaining together selected state elements of the silicon hardware into one or more scan chains (Step 50). For example, the scan chains may be logical networks of flip-flops, which can be stimulated during testing. Then, testing is initiated (Step 52). At one or more appropriate points during testing, the test is halted (Step 54), and the contents of the scan chain shifted out (Step 56). The values of state elements are the contents of the scan chain.
A varying period of time may be required in order to shift out the contents of the scan chain, depending on implementation. For example, it may require 1 millisecond to shift out 5000 state element values at 100 MHZ. Thus, if there are 50 shifts, 5 seconds may be required. Furthermore, testing using scan chains may require coordination between control of a clock for the silicon hardware, and control of a clock for the scan chain.
Once the contents of the scan chain(s) are shifted out, the bit values (i.e., “1” or “0” of the state elements) are examined (Step 58). Testing is then completed (Step 60). Those skilled in the art will appreciate that validation of silicon hardware through testing is generally an iterative process, and that the process shown in FIG. 2 may be performed multiple times, with, or without additional steps.
Even after the silicon hardware has been shipped to customers, testing may not be complete. Many computing devices that include the silicon hardware requires execution of diagnostic tests during initial boot up. The diagnostic tests typically check silicon hardware components, such as checking memory circuits for faults. Often, even powerful computer systems are “resource poor” during the early phases of booting up.
To conserve resources during boot up, most diagnostic tests are self-checking. During the self-checking tests, diagnostic test results are typically computed using two different implementations, and then a test result is determined from comparing results from the two different implementations. Often, one of the implementations is significantly slower than the other implementation. In any case, the self-checking diagnostic test takes at least twice the time of the shorter implementation. It should be noted that under test conditions, computing environments may not only be resource poor, but also, time limited (i.e., only a short amount of time is allocated to running diagnostics before allowing a user access to the computer system).